1. Field of the Invention
This invention relates to cache memory subsystems, and more particularly, to sense amplifier multiplexer latch designs.
2. Description of the Related Art
In some cache memory designs, the cache may include two or more banks of memory. Each bank may be a memory array of rows and columns of memory cells. The rows may be accessed by a word select control circuit and the columns in a row may provide output values via a pair of bit lines per column. Upon a memory read, one bank may be selected and the bit lines corresponding to a particular memory cell in that bank may transmit the value in the cell to a sense amplifier. The bit lines are typically differential outputs to the sense amplifier. The two differential outputs are sometimes referred to as a xe2x80x9cbitxe2x80x9d signal and a xe2x80x9cbit barxe2x80x9d signal. The bit lines may carry voltages corresponding to a binary value stored in one of the bit cells within the cache array. Particularly, the memory cell may develop a relatively small differential on the bit lines to indicate the binary value stored (e.g. on the order of 100 millivolts). The sense amplifiers may sense the differential voltage on the bit lines and amplify the sensed differential voltage on a pair of output lines of the sense amp such that one output line may carry a high voltage (e.g. VDD) and the other output line may carry a low voltage (e.g. ground). The sense amplifiers"" differential output may be precharged to a known value prior to any output lines becoming active. The precharging may occur during one phase of a clock while the output lines may be active during another phase of the clock. In this case, it may be necessary to capture or latch the sense amplifier outputs prior to the output lines being precharged during a subsequent clock phase.
Each of the above-mentioned banks of memory may include sense amplifiers for providing outputs from that bank. Since only one bank is typically read during a memory read, the outputs from the banks of the cache are typically multiplexed to provide read data from a single bank as the output from the cache to circuitry receiving the read data. Thus, the multiplexer must typically receive the bank select control signal to select the output data.
A bank select multiplexer latch circuit may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. In one embodiment, a first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active. A latching circuit including a first inverter and a second inverter is coupled to the first output node and the second output node and configured to retain the first output on the first output node and the second output on the second output node.
Broadly speaking, in one embodiment, a circuit is contemplated comprising a first subcircuit including a first N-channel transistor and a second N-channel transistor. The first subcircuit is coupled to receive at least a first input signal and a second input signal. The first subcircuit is also configured to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. The circuit also comprises a second subcircuit including a third N-channel transistor and a fourth N-channel transistor. The second subcircuit is coupled to receive at least a third input signal and a fourth input signal. The second subcircuit is also configured to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active. Additionally, the circuit further comprises a latching circuit including a first inverter and a second inverter. The latching circuit is coupled to the first output node and the second output node. The latching circuit is configured to capture and retain the first output on the first output node and the second output on the second output node.
In other embodiments the circuit may include a third subcircuit coupled receive the first, second, third and fourth input signals and coupled to the first and second output nodes. The third subcircuit is also configured to drive a third output on the second output node responsive to either one of the first input signal or the second input signal being active. The third subcircuit is configured to drive a fourth output on the first output node responsive to either one of the third input signal or the fourth input signal being active.
In an alternative embodiment, a circuit is contemplated comprising a first circuit coupled to receive a first pair of differential data inputs and a second pair of differential data inputs. The first circuit is coupled to a pair of differential output nodes and is configured to capture and retain an output on the pair of differential output nodes responsive to a corresponding one of the first pair of differential data inputs or the second pair of differential data inputs being active. A second circuit is also contemplated including a first NOR gate, a first P-Channel transistor, a second NOR gate and second P-channel transistor. The second circuit is connected in parallel to the first circuit and is configured to drive an output on the pair of differential output nodes responsive to a corresponding one of the first pair of differential data inputs or the second pair of differential data inputs being active. In addition, the first NOR gate is coupled to receive a first input signal from the first pair of differential data inputs and a second input from the second pair of differential data inputs. The second NOR gate is coupled to receive a third input signal from the first pair of differential data inputs and a fourth input signal from the second pair of differential data inputs.
In addition, a method of operating a circuit is contemplated. In one embodiment, the circuit receives a first input signal, a second input signal, a third input signal and a fourth input signal. The circuit drives a differential output on a first output node and a second output node responsive to the first input signal, the second input signal, the third input signal and the fourth input signal being active. Furthermore, the circuit retains the differential output on the first output node and the second output node responsive to the first input signal, the second input signal, the third input signal and the fourth input signal becoming inactive.